paxkid.blogg.se - Verilog linear feedback shift register

Look to the comments within the module for further guidance. The size of the LFSR used for clocking can be changed by changing the generic “V” value in the module’s entity. The type of output distribution can be selected. The output word width can be scaled from 4 to 24 bits. The LFSR_Plus.v can be configured by changing the values within the generic parameters within the module’s entity block.

Lattice Diamond Design Software version 2.0.1 with third party software Synplify Pro for Lattice and Active-HDL Lattice Edition.

The Software required/used for this design: The polynomials used are commented in the Verilog module. As the output-width is scaled, a different LFSR is built with a polynomial to provide maximal length. This function is chosen to provide a maximally long sequence. The LFSR is a shift register of arbitrary length that takes its input based off a linear function derived from the previous state. This example uses the Excel statistical add-in package to generate histograms. This data can be entered into one’s favorite statistical analysis software package for verification. The LFSR_Plus.v module is verified in a test bench by writing out the pseudo-random values to a file.

Sample histograms are included in the figures following. These distributions are created by altering a scalable LFSR output by clocking the output irregularly with a non-uniform clock, shifting scaled outputs into a buffer-adder-tree to effectively use the central limit theorem to create a normal distribution, and a feedback loop to further shape the distributions. The module gives the user 4 options for output distribution types, Gaussian unimodal, bimodal, uniform, and non-uniform distributions. This Verilog module uses 2 Linear Feedback Shift Registers (LFSR) with polynomials for maximal sequence length, one of which is scalable to output word size (4 to 24 bit) and one to operate as a non-uniform duty cycle clock. Writing Pseudo Random Numbers to File using a Test Bench (Verilog Test Fixture) Introduction.

Sample output distributions (Histograms).Basic LFSR_Plus.v Core options and configuration.Using Central Limit Theorem and feedback to shape distribution.Overview of the Linear Feedback Shift Register.The following topics are covered using the Lattice Diamond Design Software version 2.0.1.